Month: December 2013

Architecting 3D Memory Systems

Moin Qureshi
Georgia Tech
Abstract: 
Die stacked 3D DRAM technology can provide low-energy high-bandwidth memory module by vertically integrating several dies within the same chip. However, the size of such 3D memory modules is unlikely to be sufficient to provide the full memory capacity required for typical systems, so future memory systems are likely to use 3D DRAM together with traditional off-chip DRAM. In this talk, I will discuss how such memory systems can efficiently architect 3D DRAM either as a cache or as main memory. First, I will show that some of the basic design decisions typically made for conventional caches (such as serialization of tag and data access, large associativity, and update of replacement state) are detrimental to the performance of DRAM caches, as they exacerbate hit latency. I will present Alloy Cache, a simple latency-optimized DRAM cache architecture that can outperform even an impractical SRAM Tag-Store design, which would incur an unacceptable overhead of several tens of megabytes. Finally, I will present a memory organization that allows 3D DRAM to be a part of the OS-visible memory address space, and yet relieves the OS from data migration duties. The proposed CAMEO (CAche-like MEmory Organization) design performs data migration between off-chip memory and 3D DRAM at a line-size granularity, in a manner transparent to the OS. CAMEO outperforms using 3D DRAM only as a cache or only as a OS-managed two-level memory.
Speaker Biography: 
Dr. Moinuddin Qureshi joined the faculty of the Georgia Institute of Technology as anAssociate Professor in August 2011. His research interests include computer architecture, scalable memory systems, fault tolerant computing, and analytical modeling of computer systems. He worked as a research staff member at IBM T.J. Watson Research Center from 2007 to 2011. While at IBM, he contributed to the design of efficient caching algorithms for Power 7 processors. He was awarded the IBM outstanding technical achievement award for his studies on emerging memory technologies for server processors. He is a recipient of the NetApp Faculty Fellowship (2012) and Intel Early Career Faculty Award (2012). He received his Ph.D. (2007) and M.S. (2003), both in Electrical Engineering from the University of Texas at Austin, and his Bachelor of Electronics Engineering (2000) degree from University of Mumbai.

New Directions in Memory Architecture

Hongzhong Zheng
Samsung
Abstract: 
Demand is rapidly escalating for higher-performing, more energy-efficient memory and storage for applications ranging from mobile devices to the cloud. This has serious implications for the open server platform. DRAM faces a major overhaul that will demand new system architectures. Meanwhile, V-NAND, a vertical 3-D NAND flash technology, is offering both higher endurance and smaller cell sizes, in leading the way to substantive changes in system design. Furthermore, other technologies are on the horizon that together will enable a new generation of “persistent” memory devices. They will have even higher performance than today’s devices and will enable a new tier in both memory and storage architectures.
Speaker Biography: 
Hongzhong Zheng received the BS and MS degrees in electrical engineering and computer science from Huazhong University of Science and Technology, China, and the PhD degree in electrical and computer engineering from the University of Illinois at Chicago in 2009. He is currently a memory system architect at System Architecture Labs of Samsung Semiconductor Inc. He has extensive experience of novel memory system architecture with DRAM and emerging memory technologies, computer architecture and system performance modeling, energy-efficient computing system designs etc. He had more than 15 patents (including issued and pending applications), and more than 10 peer reviewed papers published in top journals and conferences. He is a member of the ACM and the IEEE.