Month: January 2014

Error Management and Control For Data-Center Based Next-Generation Solid State Drives

Stephen Bates
There can be no doubt that NAND flash based Solid State Drives (SSDs) are having a massive impact on the design and implementation of data-centers. SSDs allow data-centers to accelerate applications that are deployed as cloud services as well as providing a low latency tier of storage and reducing the Total Cost of Ownership (TCO) of the data-center infrastructure. The huge demand for flash by data-center vendors and cloud service providers is tempered only by the cost per GB for an SSD. As such, there is huge pressure on SSD vendors to produce high capacity, high endurance SSDs for less cost. One way to achieve this goal is to use smaller lithography flash to permit more bits per unit area and hence less cost per bit. However as one scales down NAND flash the endurance of the flash tends to also drop. We can compensate for this by using more advanced error correction and media management techniques and for this reason. In this talk we will look at the trends in NAND flash and SSDs with regard to keeping SSDs on this downward trend in terms of cost per bit. We will look at schemes such as LDPC error correcting codes and how they can increase the endurance of an SSD whilst also reducing the cost of the SSD.
Speaker Biography: 
Stephen Bates received a 1st class BEng from the University of Edinburgh and a PhD from the same institution in 1994 and 1997 respectively. His PhD investigated the impact of self-similarity in the traffic that traverses computer networks and on the design of switches for such networks. Stephen joined Massana Ltd, in Dublin, Ireland in 1997. Massana developed physical layer solutions for the 1000BASE-T Gigabit Ethernet standard. Stephen was an architect for the signal processing sections of this PHY and as such worked on problems such as error correction, echo cancellation, timing recovery and channel equalization. In September 2003 Stephen joined the University of Alberta’s department of Electrical and Computer Engineering as an assistant professor. His research focused on bridging the domain between algorithm development and silicon implementation. He has published a number of papers in IEEE journals and at international conference. Stephen is currently a Technical Director in the Chief Strategy and Technology Office of PMC-Sierra. He works on defining PMCs product strategy and works with the Business Units at PMC to define and design their next-generation products. Stephen is also responsible for identifying key emerging technologies and assisting in mergers and acquisitions. Stephen is a Senior Member of the IEEE and a Professional Engineer of Canada.